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Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
FEATURES
* 1 LVCMOS / LVTTL output * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 350MHz (typical) * Part-to-part skew: 500ps (maximum) * Small 8 lead SOIC package saves board space * Full 3.3V, 2.5V operating supply * -40C to 85C ambient operating temperature * Lead-Free fully RoHS compliant
GENERAL DESCRIPTION
T h e I C S 8 3 021I i s a 1 - t o -1 Differential-toLVCMOS/LVTTL Translator and a member of the HiPerClockSTM HiPerClockSTMfamily of High Perfor mance Clock Solutions from ICS. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
ICS
BLOCK DIAGRAM
CLK nCLK Q0
PIN ASSIGNMENT
nc CLK nCLK nc 1 2 3 4 8 7 6 5 VDD Q0 nc GND
ICS83021I
8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View
83021AMI
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Type Unused Input Input Power Output Power Pullup Description No connect. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 4, 6 2 3 5 7 8 Name nc CLK nCLK GN D Q0 VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 VDD = 3.6V 23 51 51 7 12 Maximum Units pF pF k k
83021AMI
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V0.3V or 2.5V5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 2.375 Typical 3.3 2.5 Maximum 3.6 2.625 20 Units V V mA
TABLE 3BC. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V0.3V or 2.5V5%, TA = -40C TO 85C
Symbol VOH Parameter Output High Voltage; NOTE 1 Test Conditions VDD = 3.6V VDD = 2.625V Minimum 2.6 1.8 Typical Maximum Units V V V
Output Low Voltage; NOTE 1 0.5 VOL NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, Output Load Test Circuit Diagrams.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V0.3V or 2.5V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VDD = 3.6V or 2.625V VIN = VDD = 3.6V or 2.625V VIN = 0V, VDD = 3.6V or 2.625V VIN = 0V, VDD = 3.6V or 2.625V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Test Conditions 350MHz 0.8V to 2V 166MHz Minimum 1. 7 100 45 Typical 350 2. 0 250 50 2.3 500 400 55 Maximum Units MHz ns ps ps % %
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay, NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle
tsk(pp)
tR / tF odc
166MHz < 350MHz 40 50 60 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay, NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 250MHz 250 45 50 350MHz 1.9 Test Conditions Minimum Typical 350 2.2 2.5 500 550 55 Maximum Units MHz ns ps ps % %
tsk(pp)
tR / tF odc
250MHz < 350MHz 40 50 60 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
83021AMI
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V 1.25V 5%
V DD
Qx
SCOPE
VDD
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 0.15V
-1.25V 5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1 Qx
V
DD
2
nCLK
V
CLK
PP
Cross Points
V
PART 2 Qy
V
CMR
DD
2 tsk(pp)
GND
DIFFERENTIAL INPUT LEVEL
nCLK CLK
PART-TO-PART SKEW
V Q0 Pulse Width t
DD
2
Q0
VDD 2 t
PERIOD
PD
odc =
t PW t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
2V 0.8V tR
2V 0.8V tF 20%
80%
80% 20%
Clock Outputs
Clock Outputs
tR
tF
3.3V OUTPUT RISE/FALL TIME
83021AMI
2.5V OUTPUT RISE/FALL TIME
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83021I is: 416 Pin-to-pin compatible with MC100EPT21
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Marking 83021AMI 83021AMI 83021AIL 83021AIL Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83021AMI ICS83021AMIT ICS83021AMILF ICS83021AMILFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83021AMI
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REV. B MARCH 21, 2005
Integrated Circuit Systems, Inc.
ICS83021I
1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
REVISION HISTORY SHEET Description of Change Pin Characteristics table - added 2.5V CPD. Added 2.5V Power Supply table. LVCMOS table - added 2.5V VOH. Differential table - added 2.5V. Added 2.5V AC Characteristics table. Added 2.5V Output Load AC Test Circuit Diagram and 2.5V Output Rise/Fall Time Diagrams. Updated Figure 1. Added Differential Clock Input Interface section. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. 3.3V AC Characteristics Table - changed odc Test Conditions. Features Section - added Lead-Free bullet. Ordering Information Table - Added Lead-Free par t number. Date
Rev
B
Table T2 T3B T3C T3D T4B
Page 2 3 3 3 4 5 6 7 2 4 1 10
6/3/04
B B
T4A T7
6/30/04 3/21/05
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